1. Field of the Invention
The present invention relates to a technology of a built-in self test (BIST) and a pseudorandom number generator.
2. Description of the Related Art
In recent years, as a test method for a semiconductor integrated circuit, a BIST using a pseudorandom number generator, such as a linear feedback shift register (LFSR) is utilized for the purpose of, for example, reducing test time.
FIG. 12 is a schematic of a circuit configuration of an LFSR according to a conventional technology. As shown in FIG. 12, an LFSR 1200 has a four-bit shift register mainly using flip-flops (F/F) formed therein. An XOR circuit that feeds back an exclusive OR of a first bit and a last bit to the first bit is also provided.
Like the LFSR 1200, the use of an n-bit shift register enables output of a test pattern having a maximum cycle of 2n-1. For example, as shown in FIG. 12, the LFSR 1200, being a four-bit shift register, enables output of a test pattern of 15 phases. As shown in FIG. 12, when seed values “1101” are set sequentially starting from the first bit in the shift register, the LFSR 1200 can output a test pattern “101100100011 . . . ”.
FIG. 13 is a schematic of a circuit configuration of a circuit under test including an LFSR according to a conventional technology. As shown in FIG. 13, a circuit-under-test 1300 includes the LFSR 1200 depicted in FIG. 12, scan paths 1310, 1320, 1330, and 1340 formed of plural of F/Fs, and an output verifier, e.g., a multiple input signature register (MISR) 1350.
When a BIST is performed on the circuit-under-test 1300, an external control signal is first input to set seed values of the LFSR 1200. Based on the input of the external control signal, a control signal is supplied to the LFSR 1200 resulting in values of a test pattern output from the LFSR 1200 to be sequentially input into the first F/Fs in the respective scan paths 1310 to 1340. Subsequently, values stored in the F/Fs are output at each system clock, and output results from each of the scan paths 1310 to 1340 are compressed and stored in the MISR 1350.
Providing the LFSR 1200 in the circuit-under-test 1300 in this manner enables the BIST of the circuit-under-test 1300 to be performed using many test patterns. However, outputting test patterns from the LFSR 1200 that match test patterns having a high failure detection rate automatically generated from an automatic test pattern generator (ATPG) is a problem.
Thus, a test method of correcting each test pattern output from the LFSR based on the input of the external control signal or correcting the seed value of the LFSR to match each test pattern output from the LFSR with each test pattern having a high failure detection rate automatically generated by the ATPG (hereinafter, “ATPG pattern”) has been disclosed (see, for example, Japanese Patent Application Laid-open No. 2002-236144 and Published Japanese Translation of PCT Application No. 2003-518245). According to such a test method, the BIST using test patterns having a high failure detection rate can be efficiently carried out in a short period of time without requiring a high-capacity memory to store a large number of test patterns.
However, in the technologies disclosed in Japanese Patent Application Laid-open No. 2002-236144 and Published Japanese Translation of PCT Application No. 2003-518245, since the factor of the time (clock count) is not considered, the time required to perform the test cannot be reduced in view of the time involved for the correction of the test patterns.
FIG. 14 is a schematic of a test pattern matching method according to a conventional technology. For example, as shown in FIG. 14, when an ATPG pattern is “10X1100X10 . . . ”, (1) a seed value “1101” is set with respect to the LFSR. At this time, a clock count of 4 is required. As a result, a test pattern is temporarily determined as “101100100011110 . . . ”. (2) Then, the LFSR is shifted for four bits that are matched with the ATPG pattern. At this time, a clock count of 4 is required.
(3) Subsequently, seed values “0001” are again set with respect to the LFSR. At this time, a clock count of 4 is required. (4) The LFSR is shifted for five bits that are matched with the ATPG pattern. At this time, a clock count of 5 is required. (5) A seed value “0 . . . ” is again set with respect to the LFSR. At this time, a clock count of 4 is required. A clock count required for the processing (1) to (5) is 21.
When the seed value is again set with respect to the four-bit shift register in this manner, a control signal having at least a clock count of 4 is required. Therefore, the time required for testing cannot be reduced in view of the clock count involved in correction of the test pattern.